The present invention relates to logic simulation, and more particularly to a logic simulation which is well suited to simulate the behavior of a logic device in terms of register-transfer levels.
Heretofore, the selective trace technique and the selective event technique have been known for executing logic simulations at high speed, as discussed in "Advances in CAD for VLSI", Vol. 2, pp. 145-146, July, 1986. With the selective trace technique, an output value calculating process is performed for only elements whose signal values at their input pins changed, that is, as to which events occurred. Thus, it is possible to reduce the number of events to-be-processed and to sharply shorten a simulation time period. On the other hand, the selective event technique exploits the property that, in an AND gate by way of example, insofar as the signal value of at least one of the input pins thereof is "0", the output signal value thereof remains unchanged at "0" even when the signal value of any of the other input pins changes. It adopts a method wherein, even in case of the change of the signal value of any input pin, that is, the occurrence of an event, the output signal value of the element is not calculated by reason of the signal value of another input pin. Thus, it can reduce the number of events to-be-processed still more than the selective trace technique.
The demand driven simulation algorithm is stated in "24th Design Automation Conference Proceedings", pp. 181-187, June, 1987. With the demand driven simulation algorithm, unnecessary evaluations are inhibited to shorten a simulation time period by a method wherein a process is begun with any desired signal at any desired time at which a simulation result is to be obtained, and wherein signal values required for obtaining the result are successively found while the connectional relationship of a logic and the time are being backtraced or backtracked.